1. Field of the Invention
This invention relates to an improved memory architecture that decreases bitline coupling to provide increased speed and reduced power consumption. The scheme is applicable to all types of memories using multiple wordlines.
2. Discussion of the Related Art
Memory architectures are continuously targeting higher operating speeds and increased densities. The increased densitites in turn impose additional requirements of reduced power dissipation. Several efforts have been made in addressing these requirements. One approach has been to introduce a stable voltage line, generally a power line, between adjacent bitlines so as to reduce the capacitive coupling between them thereby decreasing the capacitive loading resulting in increased speed and reduced power consumption. However, this technique increases the area required by each bitcell which conflicts with the requirement of increased bit densities.
U.S. Pat. No. 6,160,730 describes a memory architecture that uses interlaced multiple wordlines and provides a local selection line which crosses the word select line and connects to only one of the word select lines. While this invention does reduce bitcell area it does not address the issue of reducing capacitance to increase speed or reduce power consumption.